document no. 70-0266-01 www.psemi.com page 1 of 7 ?2008 peregrine semiconductor corp. all rights reserved. rf2 rf1 cmos control driver and esd ctrl rfc 32-lead 5x5 mm qfn figure 2. package type the following specification defines an spdt (single pole double throw) switch for use in cellular and other wireless applications. the PE42510A uses peregrine?s ultracmos? process and it also features harp? technology enhancements to deliver high linearity and exceptional harmonics performance. harp? technology is an innovative feature of the ultracmos? process providing upgraded linearity performance. the PE42510A is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt high power ultracmos? rf switch 30 - 2000 mhz product description figure 1. functional diagram PE42510A features ? no blocking capacitors required ? 50 watt p1db compression point ? 10 watts <8:1 vswr (normal operation) ? 29 db isolation @800 mhz ? < 0.3 db insertion loss at 800 mhz ? 2f o and 3f o < -84 dbc @ 42.5 dbm ? esd rugged to 2.0 kv hbm ? 32-lead 5x5 mm qfn package table 1. electrical specifications @ 25 c, v dd = 3.3 v (z s = z l = 50 ? ) unless otherwise noted parameter conditions min typ max units rf insertion loss 30 mhz 1 ghz 1 ghz < 2 ghz 0.4 0.5 0.6 0.7 db db 0.1 db input compression point 800 mhz, 50% duty cycle 45.4 dbm isolation (supply biased): rf to rfc 800 mhz 25 29 db unbiased isolation: rf - rfc, v dd , v1=0 v 27 dbm, 800 mhz 5 db rf (active port) return loss 15 22 db 2nd harmonic 3rd harmonic 800 mhz @ +42.5 dbm -84 -81 dbc switching time 50% of ctrl to 10/90% of rf 0.04 0.5 ms lifetime switch cycles no rf applied 10^10 cycles note: the device was matched with 1.6 nh inductance per rf port
product specification PE42510A page 2 of 7 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0266-01 ultracmos? rfic solutions 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 gnd rf1 gnd gnd gnd gnd gnd gnd gnd rf2 gnd gnd gnd gnd gnd gnd gnd gnd n/c v dd ctrl gnd gnd n/c gnd gnd gnd gnd rfc gnd gnd gnd exposed ground paddle table 2. pin descriptions table 4. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. table 3. operating ranges figure 3. pin configuration (top view) pin no. pin name description 1 gnd ground 2 rf1 rf1 port 3 gnd ground 4 gnd ground 5 gnd ground 6 gnd ground 7 gnd ground 8 gnd ground 9 gnd ground 10 gnd ground 11 n/c no connect 12 v dd nominal 3.3 v supply connection 13 ctrl control 14 gnd ground 15 gnd ground 16 n/c do not connect 17 gnd ground 18 gnd ground 19 gnd ground 20 gnd ground 21 gnd ground 22 gnd ground 23 rf2 rf2 port. 24 gnd ground 25 gnd ground 26 gnd ground 27 gnd ground 28 rfc common rf port for switch 29 gnd ground 30 gnd ground 31 gnd ground 32 gnd ground paddle gnd exposed ground paddle absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. table 5. control logic truth table symbol parameter/conditions min max units v dd power supply voltage -0.3 4 v v i voltage on any dc input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t case maximum case temperature 85 c t j peak maximum junction temperature (10 seconds max) 200 c p in rf input power (vswr 20:1, 10 seconds) 40 dbm rf input power (50 ? ) 45 dbm rf input power, unbiased (vswr 20:1) 27 dbm p d maximum power dissipation due to rf insertion loss 2.2 w v esd esd voltage (hbm, mil_std 883 method 3015.7) 2000 v parameter min typ max units v dd power supply voltage 3.2 3.3 3.4 v i dd power supply current 90 170 ua control voltage high 1.4 v control voltage low 0.4 v operating temperature range (case) -40 85 c t j operating junction temperature 140 c frequency range 30 2000 mhz rf input power 1 (vswr 8:1) 40 dbm rf input power 2 (vswr 8:1) 27 dbm path ctrl rfc ? rf1 h rfc ? rf2 l moisture sensitivity level the moisture sensitivity level rating for the 5x5 qfn package is msl3. notes: 1. supply biased 2. supply unbiased
product specification PE42510A page 3 of 7 document no. 70-0266-01 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. evaluation kit the PE42510A evaluation kit board was designed to ease customer evaluation of the PE42510A rf switch. dc power is supplied through j10, with v dd on pin 9, and gnd on the entire lower row of even numbered pins. to evaluate a switch path, add or remove jumpers on ctrl/v1 (pin 3) using table 5 (adding a jumper pulls the cmos control pin low and removing it allows the on-board pull-up resistor to set the cmos control pin high). j10 pins 1, 11, and 13 are n/c. the rf common port (rfc) is connected through a 50 ohm transmission line via the top sma connector, j1. rf1 and rf2 paths are also connected through 50 ohm transmission lines via sma connectors. a 50 ohm through transmission line is available via sma connectors j8 and j9. this transmission line can be used to estimate the loss of the pcb over the environ mental conditions being evaluated. an open-ended 50 ohm transmission line is also provided at j7 for calibration if needed. figure 4. evaluation board layouts figure 5. evaluation board schematic peregrine specification 102/0383 peregrine specification 101/0314 open line through line pe42510 u1 qfn5x5-32ld u1 qfn5x5-32ld nc 1 rf1 2 nc 3 nc 4 nc 5 gnd 6 nc 7 nc 8 nc 9 nc 10 (res) 11 vd d 12 v1 13 nc 14 nc 15 (vss) 16 nc 17 gnd 18 nc 19 nc 20 nc 21 nc 22 rf2 23 nc 24 gnd 25 nc 26 nc 27 rfc 28 nc 29 nc 30 nc 31 gnd 32 r1 1 m r1 1 m c7 100pf c7 100pf j2 sm a j2 sm a 1 2 c8 0.01u c8 0.01u j3 sm a j3 sm a 1 2 c2 dni c2 dni j8 sm a - d ni j8 sm a - d ni 1 2 j9 sm a - d ni j9 sm a - d ni 1 2 j1 sm a j1 sm a 1 2 c3 dni c3 dni j10 header 14 j10 header 14 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 c4 0.01u c4 0.01u j7 sm a - d ni j7 sm a - d ni 1 2 z1 z1 1
product specification PE42510A page 4 of 7 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0266-01 ultracmos? rfic solutions figure 7. rf-rfc insertion loss, +25 c figure 6. rf-rfc insertion loss, v dd = 3.3v figure 8. rfc-rf isolation, v dd = 3.3v figure 9. rfc-rf isolation, +25 c figure 11. rf return loss, +25 c figure 10. rf return loss, v dd = 3.3v
product specification PE42510A page 5 of 7 document no. 70-0266-01 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. figure 12. power dissipation figure 13. maximum junction temperature thermal data though the insertion loss for this part is very low, when handling high power rf signals, the part can get quite hot. figure 12 shows the estimated power dissipation for a given incident rf power level. multiple curves are presented to show the effect of poor vswr conditions. vswr conditions t hat present short circuit loads to the part can cause significantly more power dissipation than with proper matching. figure 13 shows the estimated maximum junction temperature of the part for similar conditions. note that both of these charts assume that the case (gnd slug) temperature is held at 85c. special consideration needs to be m ade in the design of the pcb to properly dissipate the heat away from the part and maintain the 85c maximum case temperature. it is recommended to use best design practices for high power qfn packages: multi-layer pcbs with thermal vias in a thermal pad soldered to the slug of the package. special care also needs to be made to alleviate solder voiding under the part. table 6. theta jc parameter min typ max units theta jc (+85c) 24.0 c/w 85 90 95 10 0 10 5 110 115 12 0 12 5 13 0 13 5 14 0 14 5 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 rf power (dbm) max junction temperature (c) 1:1 vswr (50 ohm load) 2:1 vswr (25 ohm load) 8:1 vswr (6.25 ohm load) 20:1 vswr (2.5 ohm load) inf:1 vswr (0 ohm load) reliability limit 0.0 0.5 1. 0 1. 5 2.0 2.5 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 rf po w e r ( d bm ) power dissipated (w) 1:1 vswr (50 ohm load) 2:1 vswr (25 ohm load) 8:1 vswr (6.25 ohm load) 20:1 vswr (2.5 ohm load) inf:1 vswr (0 ohm load) reliability limit note: case temperature = 85c
product specification PE42510A page 6 of 7 ?2008 peregrine semiconductor corp. all rights reserved. document no. 70-0266-01 ultracmos? rfic solutions table 7. ordering information order code part mark ing description package shipping method PE42510Amli 42510 parts in tubes or cut tape green 32-lead 5x5mm qfn 73 units / tube PE42510Amli-z 42510 parts on tape and r eel green 32-lead 5x5mm qfn 3000 units / t&r ek42510-01 42510 evaluation kit evaluation kit 1 / box figure 14. package drawing figure 15. tape and reel specs note: not for electrical connection. corner detail is tied to paddle and should not be isolated on pcb board. see note below
product specification PE42510A page 7 of 7 document no. 70-0266-01 www.psemi.com ?2008 peregrine semiconductor corp. all rights reserved. sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at an y time without notice in order to supply the best possible product. product specification the data sheet contains final dat a. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a dcn (document change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which persona l injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental dam ages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp and multiswitch are trademarks of peregrine semiconductor corp. space and defense products americas: tel: 858-731-9453 europe, asia pacific: 180 rue jean de guiramand 13852 aix-en-provence cedex 3, france tel: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213
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